1. Field of the Invention
The invention relates to the field of precision-controlled duty cycle clock circuits for use with electronic devices. More specifically, the invention provides a circuit having an adaptive adjustment to improve the controllability of the duty cycle of an output clock signal in response to the changing characteristics of an input clock signal. The invention finds application in a variety of electronic devices, including wireless communications devices.
2. Description of the Related Art
Many high performance clocked digital circuits require a clock signal with a precisely controlled duty cycle. These types of circuits may use both the high and low phases of the clock signal to perform computations. If, for example, a circuit has the same timing requirements for both the high and low phase of the clock signal, then a clock signal with an accurate 50/50 duty cycle yields the maximum amount of time in each phase of the clock signal for any given frequency. Clock sources with less accurate control over their duty cycle would have to operate at a lower frequency to meet the timing requirements of such a circuit. Hence, clock circuits providing accurate duty cycle control allow either a higher clock rate or a lower core voltage, while still maintaining adequate timing margin for circuits operating from both phases of the clock signal.